ST STM32G4 Series Reference Manual page 686

Analog-to-digital converters (ADC)
End of sequence of conversions of an injected group
Analog watchdog 1 status bit is set
Analog watchdog 2 status bit is set
Analog watchdog 3 status bit is set
End of sampling phase
Overrun
Injected context queue overflows
686/2126
Table 174. ADC interrupts per each ADC (continued)
Interrupt event
RM0440 Rev 4
Event flag Enable control bit
JEOS JEOSIE
AWD1 AWD1IE
AWD2 AWD2IE
AWD3 AWD3IE
EOSMP EOSMPIE
OVR OVRIE
JQOVF JQOVFIE
RM0440