Table 123. Programmable Nor/Psram Access Parameters; Table 124. Non-Multiplexed I/O Nor Flash Memory - ST STM32G4 Series Reference Manual

RM0440
Parameter
Address
setup
Address hold
NBL setup
Data setup
Data hold
Bust turn
Clock divide
ratio
Data latency
19.6.1 External memory interface signals
Table 124,
NOR Flash memory, SRAM and PSRAM.
Note: The prefix "N" identifies the signals that are active low.
NOR Flash memory, non-multiplexed I/Os
The maximum capacity is 512 Mbits (26 address lines).

Table 123. Programmable NOR/PSRAM access parameters

Function
Duration of the address
setup phase
Duration of the address hold
phase
Duration of the byte lanes
setup phase
Duration of the data setup
phase
Duration of the data hold
phase
Duration of the bus
turnaround phase
Number of AHB clock cycles
(HCLK) to build one memory
clock cycle (CLK)
Number of clock cycles to
issue to the memory before
the first data of the burst
Table 125 and Table 126

Table 124. Non-multiplexed I/O NOR Flash memory

FMC signal name
CLK
A[25:0]
D[15:0]
NE[x]
NOE
NWE
NL(=NADV)
NWAIT
Flexible static memory controller (FSMC)
Access mode
Asynchronous
Asynchronous,
muxed I/Os
Asynchronous
Asynchronous
Asynchronous
Asynchronous and
synchronous read
/ write
Synchronous
Synchronous
list the signals that are typically used to interface with
I/O
O
O
I/O
O
O
O
Latch enable (this signal is called address
O
valid, NADV, by some NOR Flash devices)
I NOR Flash wait input signal to the FMC
RM0440 Rev 4
Unit
AHB clock cycle
(HCLK)
AHB clock cycle
(HCLK)
AHB clock cycle
(HCLK)
AHB clock cycle
(HCLK)
AHB clock cycle
(HCLK)
AHB clock cycle
(HCLK)
AHB clock cycle
(HCLK)
Memory clock
cycle (CLK)
Function
Clock (for synchronous access)
Address bus
Bidirectional data bus
Chip select, x = 1..4
Output enable
Write enable
Min. Max.
0 15
1 15
0 3
1 256
0 3
0 15
2 16
2 17
521/2126
571