Figure 184. Timer A - ST STM32G4 Series Reference Manual

RM0440
27.3.4 Timer A..F timing units
The HRTIM embeds 6 identical timing units made of a 16-bit up-counter with an auto-reload
mechanism to define the counting period, 4 compare and 2 capture units, as per
Each unit includes all control features for 2 outputs, so that it operates as a standalone
timer.
f Prescaler
HRTIM
RST
Reset
Management
Register
The period and compare values must be within a lower and an upper limit related to the
high-resolution implementation and listed in
•
The minimum value must be greater than or equal to 3 periods of the f
value 0x0000 can be written in CMP1 and CMP3 registers only, to skip a PWM pulse.
See
•
The maximum value must be less than or equal to 0xFFFF - 1 periods of the f
clock.
Figure 184. Timer A..F overview
Capture 1
Capture 2
Counter
Compare 1
Compare 2
Compare 3
Compare 4
Denotes a register with preload
Interrupt / DMA request
Section : Null duty cycle exception case
CPT1
Repetition
CPT2
Counter
Period
CMP1
Half
CMP2
Autodelay
CMP3
CMP4
Autodelay
Table 214:
for details
RM0440 Rev 4
High-resolution timer (HRTIM)
REP
Master Other
Master
Master
Master
timer timing units
timer
timer
timer
6
9
Set / reset
REP
crossbar
CMP1
(2 outputs)
CMP2
CMP3
Push-pull
CMP4
and deadtime
Update
management
Events
Blanking and
windowing
10
From external events
conditioning
HRTIM
Figure 184.
Out 1
To the
output
Out 2
stage
MS32258V1
clock. The
HRTIM
855/2126
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