ST STM32G4 Series Reference Manual page 1214

Advanced-control timers (TIM1/TIM8/TIM20)
28.6.24 TIMx timer deadtime register 2 (TIMx_DTR2)(x = 1, 8, 20)
Address offset: 0x054
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:18 Reserved, must be kept at reset value.
Bit 17 DTPE: Deadtime preload enable
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
Bit 16 DTAE: Deadtime asymmetric enable
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 DTGF[7:0]: Dead-time falling edge generator setup
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
1214/2126
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
0: Deadtime value is not preloaded
1: Deadtime value preload is enabled
(LOCK bits in TIMx_BDTR register).
0: Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register
1: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is
defined with DTGF[7:0] bits.
(LOCK bits in TIMx_BDTR register).
This bit-field defines the duration of the dead-time inserted between the complementary
outputs, on the falling edge.
DTGF[7:5]=0xx => DTF=DTGF[7:0]x t
DTGF[7:5]=10x => DTF=(64+DTGF[5:0])xt
DTGF[7:5]=110 => DTF=(32+DTGF[4:0])xt
DTGF[7:5]=111 => DTF=(32+DTGF[4:0])xt
Example if T =125ns (8MHz), dead-time possible values are:
DTS
0 to 15875 ns by 125 ns steps,
16 us to 31750 ns by 250 ns steps,
32 us to 63us by 1 us steps,
64 us to 126 us by 2 us steps
(LOCK bits in TIMx_BDTR register).
24 23 22
Res. Res. Res.
8 7 6
Res.
rw rw
with t =t
dtg dtg
with T
dtg
with T
dtg
with T
dtg
RM0440 Rev 4
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
DTGF[7:0]
rw rw rw rw
.
DTS
=2xt .
dtg DTS
=8xt .
dtg DTS
=16xt .
dtg DTS
RM0440
17 16
DTPE DTAE
rw rw
1 0
rw rw