Table 154. Fmc Register Map And Reset Values - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus
Hide thumbs Also See for STM32G4 Series:
Table of Contents

Advertisement

Flexible static memory controller (FSMC)
19.7.8
FMC register map
Offset
Register
FMC_BCR1
0x00
Reset value
FMC_BCR2
0x08
Reset value
FMC_BCR3
0x10
Reset value
FMC_BCR4
0x18
Reset value
FMC_BTR1
0x04
Reset value
0
FMC_BTR2
0x0C
Reset value
0
FMC_BTR3
0x14
Reset value
0
FMC_BTR4
0x1C
Reset value
0
FMC_
PCSCNTR
0x20
Reset value
570/2126

Table 154. FMC register map and reset values

NBL
SET
[1:0]
0
0
NBL
SET
[1:0]
0
0
NBL
SET
[1:0]
0
0
NBL
SET
[1:0]
0
0
DATLAT[3:0]
CLKDIV[3:0]
0
0
0
1
1
1
1
1
1
DATLAT[3:0]
CLKDIV[3:0]
0
0
0
1
1
1
1
1
1
DATLAT[3:0]
CLKDIV[3:0]
0
0
0
1
1
1
1
1
1
DATLAT[3:0]
CLKDIV[3:0]
0
0
0
1
1
1
1
1
1
CPSIZE
[2:0]
0
0
0
0
0
0
0
0
CPSIZE
[2:0]
0
0
0
0
0
0
CPSIZE
[2:0]
0
0
0
0
0
0
CPSIZE
[2:0]
0
0
0
0
0
0
BUSTURN
[3:0]
1
1
1
1
1
1
1
1
BUSTURN
[3:0]
1
1
1
1
1
1
1
1
BUSTURN
[3:0]
1
1
1
1
1
1
1
1
BUSTURN
[3:0]
1
1
1
1
1
1
1
1
0
0
0
0
0
0
RM0440 Rev 4
MWID
1
1
0
0
0
1
MWID
1
1
0
0
0
1
MWID
1
1
0
0
0
1
MWID
1
1
0
0
0
1
DATAST[7:0]
ADDHLD[3:0] ADDSET[3:0]
1
1
1
1
1
1
1
1
DATAST[7:0]
ADDHLD[3:0] ADDSET[3:0]
1
1
1
1
1
1
1
1
DATAST[7:0]
ADDHLD[3:0] ADDSET[3:0]
1
1
1
1
1
1
1
1
DATAST[7:0]
ADDHLD[3:0] ADDSET[3:0]
1
1
1
1
1
1
1
1
CSCOUNT[15:0]
0
0
0
0
0
0
0
0
RM0440
MTYP
[1:0]
[1:0]
0
1
1
0
1
1
MTYP
[1:0]
[1:0]
0
1
0
0
1
0
MTYP
[1:0]
[1:0]
0
1
0
0
1
0
MTYP
[1:0]
[1:0]
0
1
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0

Hide quick links:

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the STM32G4 Series and is the answer not in the manual?

Table of Contents

Save PDF