ST STM32G4 Series Reference Manual page 1034

High-resolution timer (HRTIM)
Bit 10 TBRST: Timer B counter software reset
Refer to TARST description.
Bit 9 TARST: Timer A counter software reset
Setting this bit resets the timer A counter.
The bit is automatically reset by hardware.
Bit 8 MRST: Master counter software reset
Setting this bit resets the master timer counter.
The bit is automatically reset by hardware.
Bit 7 Reserved, must be kept at reset value.
Bit 6 TFSWU: Timer F software update
Refer to TASWU description.
Bit 5 TESWU: Timer E software update
Refer to TASWU description.
Bit 4 TDSWU: Timer D software update
Refer to TASWU description.
Bit 3 TCSWU: Timer C software update
Refer to TASWU description.
Bit 2 TBSWU: Timer B software update
Refer to TASWU description.
Bit 1 TASWU: Timer A software update
This bit is set by software and automatically reset by hardware. It forces an immediate transfer from
the preload to the active register and any pending update request is canceled.
Bit 0 MSWU: Master timer software update
This bit is set by software and automatically reset by hardware. It forces an immediate transfer from
the preload to the active register in the master timer and any pending update request is canceled.
27.5.53 HRTIM interrupt status register (HRTIM_ISR)
Address offset: 0x388
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
1034/2126
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
24 23 22
Res. Res. Res.
8 7 6
SYSFL
Res. Res. FLT6
r
RM0440 Rev 4
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
FLT5 FLT4 FLT3
T
r r r
RM0440
17 16
BMPE DLL
R RDY
r r
1 0
FLT2 FLT1
r r