ST STM32G4 Series Reference Manual page 966

High-resolution timer (HRTIM)
27.5.5 HRTIM master timer counter register (HRTIM_MCNTR)
Address offset: 0x010
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 MCNT[15:0]: Counter value
Holds the master timer counter value. This register can only be written when the master timer is
stopped (MCEN = 0 in HRTIM_MCR).
Note: For HR clock prescaling ratio below 32 (CKPSCCKPSC[2:0] < 5), the least significant bits of the
counter are not significant. They cannot be written and return 0 when read.
Note: The timer behavior is not guaranteed if the counter value is set above the HRTIM_MPER
register value.
27.5.6 HRTIM master timer period register (HRTIM_MPER)
Address offset: 0x014
Reset value: 0x0000 FFDF
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 MPER[15:0]: Master timer period value
This register defines the counter overflow value.
The period value must be above or equal to 3 periods of the f
CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
The maximum value is 0x0000 FFDF.
966/2126
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
MCNT[15:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
MPER[15:0]
rw rw rw
RM0440 Rev 4
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
clock, that is 0x60 if
HRTIM
RM0440
17 16
Res. Res.
1 0
rw rw
17 16
Res. Res.
1 0
rw rw