Table 211. Fault Inputs; Table 212. Hrtim Dac Triggers Connections - ST STM32G4 Series Reference Manual

RM0440
Fault channel
hrtim_in_flt1[4:1] PA12
hrtim_in_flt2[4:1] PA15
hrtim_in_flt3[4:1] PB10
hrtim_in_flt4[4:1] PB11
hrtim_in_flt5[4:1] PB0/PC7
hrtim_in_flt6[4:1] PC10
HRTIM DAC triggers
hrtim_dac_trg1
hrtim_dac_trig2
hrtim_dac_trig3
hrtim_dac_reset_trg1
hrtim_dac_step_trg1
hrtim_dac_reset_trg2
hrtim_dac_step_trg2
hrtim_dac_reset_trg3
hrtim_dac_step_trg3
hrtim_dac_reset_trg4
hrtim_dac_step_trg4
hrtim_dac_reset_trg5
hrtim_dac_step_trg5
hrtim_dac_reset_trg6
hrtim_dac_step_trg6
27.3.3 Clocks
The HRTIM must be supplied by the
clock period is evenly divided into up to 32 intermediate steps using an edge positioning
logic. All clocks present in the HRTIM are derived from this reference clock.
Definition of terms
f :
HRTIM
f :
HRCK

Table 211. Fault inputs

External Input On-chip source
FLTxSRC[1:0] = FLTxSRC[1:0] =
00
COMP2
COMP4
COMP6
COMP1
COMP3
COMP5

Table 212. HRTIM DAC triggers connections

DAC1_CH1
DAC_CH2
Yes
-
-
Yes
Yes
Yes
Yes
Yes
Yes
main HRTIM clock (hrtim_ker_ck). All subsequent clocks are derived and
synchronous with this source.
high-resolution equivalent clock. Considering the f
by 32, it is equivalent to a frequency of 170 x 32 = 5.44 GHz.
RM0440 Rev 4
External Input
FLTxSRC[1:0] =
01 10
EEV1
EEV2
EEV3
EEV4
EEV5
EEV6
DAC2_CH1
-
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
APB2 clock to offer a full resolution. The
t
HRTIM
High-resolution timer (HRTIM)
On-chip source
FLTxSRC[1:0] =
11
N/A
N/A
N/A
N/A
N/A
N/A
DAC3_CH1 DAC4_CH1
DAC3_CH2 DAC4_CH2
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
clock period division
HRTIM
Yes
-
-
Yes
Yes
Yes
Yes
Yes
Yes
t
HRTIM
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