ST STM32G4 Series Reference Manual page 1030

High-resolution timer (HRTIM)
27.5.50 HRTIM timer x external event filtering register 3 (HRTIM_TIMxEEFR3)
(x = A to F)
Address offset: Block A: 0x0F0
Address offset: Block B: 0x170
Address offset: Block C: 0x1F0
Address offset: Block D: 0x270
Address offset: Block E: 0x2F0
Address offset: Block F: 0x370
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res.
rw
Bits 31:14 Reserved, must be kept at reset value.
Bits 13:8 EEVACNT[5:0] External event A counter
This bitfield selects the external event A counter threshold. An event is considered valid when the
number of events is equal to the (EEVACNT[5:0]+1) value.
Bits 7:4 EEVASEL[3:0]: External event A Selection
This bit selects the external event A source.
0: External event 1 is used as external event A source
1: External event 2 is used as external event A source
...
9: External event 10 is used as external event A source
Others: Reserved
Bit 3 Reserved, must be kept at reset value.
Bit 2 EEVARSTM: External event A reset mode
This bit selects the external event x counter reset mode.
0: External event counter A is reset on each reset / roll-over event
1: External event counter A is reset on each reset / roll-over event only if no event occurs during last
counting period
Bit 1 EEVACRES: External event A counter reset
This bit resets the external event A counter. It is set by software and reset by hardware.
0: No action
1: External event counter A is reset
Bit 0 EEVACE: External event A counter enable
This bit enables the external event x counter.
0: External event A counter disabled
1: External event A counter enabled
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28 27 26 25
Res. Res. Res.
12 11 10 9
EEVACNT[5:0]
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
EEVASEL[3:0]
rw rw rw
RM0440 Rev 4
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
EEVA
Res.
RSTM
rw rw rw
RM0440
17 16
Res. Res.
1 0
EEVA EEVA
CRES CE
rw rw