Figure 217. Latency To External Events Falling Edge (Counter Reset And Output Set); Figure 218. Latency To External Events (Output Reset On External Event) - ST STM32G4 Series Reference Manual

High-resolution timer (HRTIM)

Figure 217. Latency to external events falling edge (counter reset and output set)

f clock
HRTIM
External Event
External Event
after internal
re-synchronisation
HRTIMER
1190
counter
HRTIMER
output
EExFAST = 0
HRTIMER
output
EExFAST = 1

Figure 218. Latency to external events (output reset on external event)

f
HRTIM
External Event
External Event
after internal
re-synchronisation
EExFAST = 0
EExFAST = 1
892/2126
2-3 cycles delay
11A0 11C0 1200
5-6 cycles delay
total latency
Minimal latency
(asynchronous path)
clock
2-3 cycles delay
HRTIMER
output
HRTIMER
output
Minimal latency
(asynchronous path)
Counter reset
1220 1240
00
3 cycles delay
Jitter-less High-resolution pulse
(Set at counter reset and reset at 0x85)
High-resolution pulse with
1 cycle pulselength jitter
(Set at counter reset and reset at 0x85)
5-6 cycles delay total
RM0440 Rev 4
20 40 60 80
RM0440
A0 C0
MS32279V1
MS32293V1