Figure 374. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36; Figure 375. Counter Timing Diagram, Internal Clock Divided By N - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus

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General-purpose timers (TIM2/TIM3/TIM4/TIM5)

Figure 374. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

Counter register

Counter overflow

Update event (UEV)

Update interrupt flag

Note: Here, center_aligned mode 2 or 3 is updated with an UIF on overflow

1. Center-aligned mode 2 or 3 is used with an UIF on overflow.

Counter register

Counter underflow

Update event (UEV)

Update interrupt flag

RM0440 Rev 4

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