Table 132. Fmc_Btrx Bitfields (Mode A); Table 133. Fmc_Bwtrx Bitfields (Mode A) - ST STM32G4 Series Reference Manual

RM0440
Bit number
3:2
1
0
Bit number
31:30
29:28
27:24
23:20
19:16
15:8
7:4
3:0
Bit number
31:30
29:28
27:24
23:20
19:16
15:8
7:4
3:0
Table 131. FMC_BCRx bitfields (mode A) (continued)
Bit name
MTYP As needed, exclude 0x2 (NOR Flash memory)
MUXEN 0x0
MBKEN 0x1

Table 132. FMC_BTRx bitfields (mode A)

Bit name
Duration of the data hold phase (DATAHLD HCLK cycles for read
DATAHLD
accesses).
ACCMOD 0x0
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the second access phase (DATAST HCLK cycles) for read
DATAST
accesses.
ADDHLD Don't care
Duration of the first access phase (ADDSET HCLK cycles) for read
accesses.
ADDSET
Minimum value for ADDSET is 0.

Table 133. FMC_BWTRx bitfields (mode A)

Bit name
Duration of the data hold phase (DATAHLD+1 HCLK cycles for write
DATAHLD
accesses).
ACCMOD 0x0
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the second access phase (DATAST HCLK cycles) for write
DATAST
accesses.
ADDHLD Don't care
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses.
ADDSET
Minimum value for ADDSET is 0.
RM0440 Rev 4
Flexible static memory controller (FSMC)
Value to set
Value to set
Value to set
529/2126
571