ST STM32G4 Series Reference Manual page 689

RM0440
21.6.2 ADC interrupt enable register (ADC_IER)
Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 JQOVFIE: Injected context queue overflow interrupt enable
This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow
interrupt.
0: Injected Context Queue Overflow interrupt disabled
1: Injected Context Queue Overflow interrupt enabled. An interrupt is generated when the JQOVF bit
is set.
Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no
injected conversion is ongoing).
Bit 9 AWD3IE: Analog watchdog 3 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt.
0: Analog watchdog 3 interrupt disabled
1: Analog watchdog 3 interrupt enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 8 AWD2IE: Analog watchdog 2 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt.
0: Analog watchdog 2 interrupt disabled
1: Analog watchdog 2 interrupt enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 7 AWD1IE: Analog watchdog 1 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog 1 interrupt.
0: Analog watchdog 1 interrupt disabled
1: Analog watchdog 1 interrupt enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 6 JEOSIE: End of injected sequence of conversions interrupt enable
This bit is set and cleared by software to enable/disable the end of injected sequence of conversions
interrupt.
0: JEOS interrupt disabled
1: JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set.
Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no
injected conversion is ongoing).
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
JQOVF
Res. AWD3IE AWD2IE AWD1IE JEOSIE JEOCIE OVRIE
IE
rw rw rw
RM0440 Rev 4
Analog-to-digital converters (ADC)
23 22 21 20
Res. Res. Res. Res.
7 6 5 4
rw rw rw rw
19 18 17
Res. Res. Res. Res.
3 2 1
EOSMP ADRDY
EOSIE EOCIE
IE
rw rw rw
689/2126
16
0
IE
rw
724