ST STM32G4 Series Reference Manual page 1331

RM0440
Bits 31:0 CCR2[31:0]: Capture/compare 2 value
29.5.21 TIMx capture/compare register 3 (TIMx_CCR3)(x = 3, 4)
Address offset: 0x03C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is
loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit
OC2PE). Else the preload value is copied in the active capture/compare 2 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on tim_oc2 output.
Non-dithering mode (DITHEN = 0)
The register holds the compare value.
Dithering mode (DITHEN = 1)
The register holds the integer part in CCR2[31:4]. The CCR2[3:0] bitfield contains the
dithered part.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (tim_ic2). The
TIMx_CCR2 register is read-only and cannot be programmed.
Non-dithering mode (DITHEN = 0)
The register holds the capture value.
Dithering mode (DITHEN = 1)
The register holds the capture in CCR2[31:0]. The CCR2[3:0] bits are reset.
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
General-purpose timers (TIM2/TIM3/TIM4/TIM5)
24 23 22
Res. Res. Res.
8 7 6
CCR3[15:0]
rw rw rw
RM0440 Rev 4
21 20 19 18
Res. Res. CCR3[19:16]
rw rw
5 4 3 2
rw rw rw rw
17 16
rw rw
1 0
rw rw
1331/2126
1343