ST STM32G4 Series Reference Manual page 972

High-resolution timer (HRTIM)
Bit 21 TCU: Timer C update
Register update is triggered by the timer C update
0: Update by timer C disabled
1: Update by timer C enabled
Note: This bit is reserved for HRTIM_TIMCCR. It is only available for HRTIM_TIMACR,
HRTIM_TIMBCR, HRTIM_TIMDCR, HRTIM_TIMECR, HRTIM_TIMFCR.
Bit 20 TBU: Timer B update
Register update is triggered by the timer B update
0: Update by timer B disabled
1: Update by timer B enabled
Note: This bit is reserved for HRTIM_TIMBCR. It is only available for HRTIM_TIMACR,
HRTIM_TIMCCR, HRTIM_TIMDCR, HRTIM_TIMECR, HRTIM_TIMFCR.
Bit 19 TAU: Timer A update
Register update is triggered by the timer A update
0: Update by timer A disabled
1: Update by timer A enabled
Note: This bit is reserved for HRTIM_TIMBCR. It is only available for HRTIM_TIMBCR,
HRTIM_TIMCCR, HRTIM_TIMDCR, HRTIM_TIMECR, HRTIM_TIMFCR.
Bit 18 TxRSTU: Timer x reset update
Register update is triggered by timer x counter reset or roll-over to 0 after reaching the period value
in continuous mode.
0: Update by timer x reset / roll-over disabled
1: Update by timer x reset / roll-over enabled
Bit 17 TxREPU: Timer x repetition update
Register update is triggered when the counter rolls over and HRTIM_REPx = 0
0: Update on repetition disabled
1: Update on repetition enabled
Bit 16 TFU: Timer F update
Register update is triggered by the timer F update
0: Update by timer F disabled
1: Update by timer F enabled
Note: This bit is reserved for HRTIM_TIMFCR. It is only available for HRTIM_TIMACR,
HRTIM_TIMBCR, HRTIM_TIMCCR, HRTIM_TIMDCR, HRTIM_TIMECR.
Bits 15:14 DELCMP4[1:0]: CMP4 auto-delayed mode
This bitfield defines whether the compare register is behaving in standard mode (compare match
issued as soon as counter equal compare), or in auto-delayed mode (see
mode).
00: CMP4 register is always active (standard compare mode)
01: CMP4 value is recomputed and is active following a capture 2 event
10: CMP4 value is recomputed and is active following a capture 2 event, or is recomputed and
active after Compare 1 match (timeout function if capture 2 event is missing)
11: CMP4 value is recomputed and is active following a capture 2 event, or is recomputed and
active after Compare 3 match (timeout function if capture event is missing)
Note: This bitfield must not be modified once the counter is enabled (TxCEN bit set).
972/2126 RM0440 Rev 4
RM0440
Section : Auto-delayed