Table 301. Output Control Bits For Complementary Tim_Oc1 And Tim_Oc1N Channels With Break; Feature (Tim16/Tim17) - ST STM32G4 Series Reference Manual

RM0440

Table 301. Output control bits for complementary tim_oc1 and tim_oc1n channels with break

Control bits
MOE bit OSSI bit OSSR bit CC1E bit CC1NE bit tim_oc1 output state
1 X
0
0
1
1. When both outputs of a channel are not used (control taken over by GPIO controller), the OIS1, OIS1N, CC1P and CC1NP
bits must be kept cleared.
Note: The state of the external I/O pins connected to the complementary tim_oc1 and tim_oc1n
channels depends on the tim_oc1 and tim_oc1n channel state and AFIO registers.

feature (TIM16/TIM17)

X 0 0
0 0 1
0 1 0
X 1 1
1 0 1
1 1 0
X X
0 0
0 1
X
1 0
1 1
General-purpose timers (TIM15/TIM16/TIM17)
Output Disabled (not driven by the timer: Hi-Z)
tim_oc1=0
tim_oc1n=0
Output Disabled (not driven
by the timer: Hi-Z)
tim_oc1=0
tim_oc1ref + Polarity
tim_oc1=tim_oc1ref XOR
CC1P
tim_oc1ref + Polarity +
dead-time
Off-State (output enabled
with inactive state)
tim_oc1=CC1P
tim_oc1ref + Polarity
tim_oc1=tim_oc1ref XOR
CC1P
Output disabled (not driven by the timer: Hi-Z)
Off-State (output enabled with inactive state)
Asynchronously: tim_oc1=CC1P, tim_oc1n=CC1NP
Then if the clock is present: tim_oc1=OIS1 and
tim_oc1n=OIS1N after a dead-time, assuming that OIS1 and
OIS1N do not correspond to tim_oc1 and tim_oc1n both in
active state
RM0440 Rev 4
(1)
Output states
tim_oc1n output state
tim_oc1ref + Polarity
tim_oc1n=tim_oc1ref XOR
CC1NP
Output Disabled (not driven by
the timer: Hi-Z)
tim_oc1n=0
Complementary to tim_oc1ref
(not tim_oc1ref) + Polarity +
dead-time
tim_oc1ref + Polarity
tim_oc1n=tim_oc1ref XOR
CC1NP
Off-State (output enabled with
inactive state)
tim_oc1n=CC1NP
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