Figure 485. Counter Timing Diagram, Internal Clock Divided By 4; Figure 486. Counter Timing Diagram, Internal Clock Divided By N - ST STM32G4 Series Reference Manual

Basic timers (TIM6/TIM7)
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag
Counter overflow
Update event (UEV)
Update interrupt flag
1452/2126

Figure 485. Counter timing diagram, internal clock divided by 4

tim_psc_ck
CEN
tim_cnt_ck
(UIF)

Figure 486. Counter timing diagram, internal clock divided by N

tim_psc_ck
tim_cnt_ck
1F
Counter register
(UIF)
0035
0036
20
RM0440 Rev 4
RM0440
0000 0001
MSv62301V1
00
MSv62302V1