ST STM32G4 Series Reference Manual page 596

Quad-SPI interface (QUADSPI)
Bits 13:12 ADSIZE[1:0]: Address size
Bits 11:10 ADMODE[1:0]: Address mode
Bits 9:8 IMODE[1:0]: Instruction mode
Bits 7:0 INSTRUCTION[7:0]: Instruction
20.5.7 QUADSPI address register (QUADSPI_AR)
Address offset: 0x0018
Reset value: 0x0000 0000
31 30 29 28
rw rw rw rw
15 14 13 12
rw rw rw rw
Bits 31:0 ADDRESS[31:0]: Address
596/2126
This bit defines address size:
00: 8-bit address
01: 16-bit address
10: 24-bit address
11: 32-bit address
This field can be written only when BUSY = 0.
This field defines the address phase mode of operation:
00: No address
01: Address on a single line
10: Address on two lines
11: Address on four lines
This field can be written only when BUSY = 0.
This field defines the instruction phase mode of operation:
00: No instruction
01: Instruction on a single line
10: Instruction on two lines
11: Instruction on four lines
This field can be written only when BUSY = 0.
Instruction to be send to the external SPI device.
This field can be written only when BUSY = 0.
27 26 25 24
ADDRESS[31:16]
rw rw rw rw
11 10 9 8
ADDRESS[15:0]
rw rw rw rw
Address to be send to the external Flash memory
Writes to this field are ignored when BUSY = 1 or when FMODE = 11 (memory-mapped
mode).
In dual flash mode, ADDRESS[0] is automatically stuck to '0' as the address should
always be even
RM0440 Rev 4
23 22 21 20
rw rw rw rw
7 6 5 4
rw rw rw rw
RM0440
19 18 17 16
rw rw rw rw
3 2 1 0
rw rw rw rw