ST STM32G4 Series Reference Manual page 1036

Advanced arm-based 32-bit mcus

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High-resolution timer (HRTIM)

HRTIM interrupt clear register (HRTIM_ICR)

Address offset: 0x38C

Reset value: 0x0000 0000

Bits 31:18 Reserved, must be kept at reset value.

Bit 17 BMPERC: Burst mode period flag clear

Writing 1 to this bit clears the BMPER flag in HRTIM_ISR register.

Bit 16 DLLRDYC: DLL Ready Interrupt flag Clear

Writing 1 to this bit clears the DLLRDY flag in HRTIM_ISR register.

Bits 15:7 Reserved, must be kept at reset value.

Bit 6 FLT6C: Fault 6 interrupt flag clear

Writing 1 to this bit clears the FLT6 flag in HRTIM_ISR register.

Bit 5 SYSFLTC: System fault interrupt flag clear

Writing 1 to this bit clears the SYSFLT flag in HRTIM_ISR register.

Bit 4 FLT5C: Fault 5 interrupt flag clear

Writing 1 to this bit clears the FLT5 flag in HRTIM_ISR register.

Bit 3 FLT4C: Fault 4 interrupt flag clear

Writing 1 to this bit clears the FLT4 flag in HRTIM_ISR register.

Bit 2 FLT3C: Fault 3 interrupt flag clear

Writing 1 to this bit clears the FLT3 flag in HRTIM_ISR register.

Bit 1 FLT2C: Fault 2 interrupt flag clear

Writing 1 to this bit clears the FLT2 flag in HRTIM_ISR register.

Bit 0 FLT1C: Fault 1 interrupt flag clear

Writing 1 to this bit clears the FLT1 flag in HRTIM_ISR register.

RM0440 Rev 4

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