Table 137. Fmc_Bcrx Bitfields (Mode C); Table 138. Fmc_Btrx Bitfields (Mode C) - ST STM32G4 Series Reference Manual

Flexible static memory controller (FSMC)
Bit number
31:24
23:22
20
19
18:16
15
14
13
12
11
10
9
8
7
6
5:4
3:2
1
0
Bit number
31:30
29:28
27:24
23:20
19:16
15:8
7:4
3:0
534/2126

Table 137. FMC_BCRx bitfields (mode C)

Bit name
Reserved 0x000
NBLSET[1:0] Don't care
CCLKEN As needed
CBURSTRW 0x0 (no effect in Asynchronous mode)
CPSIZE 0x0 (no effect in Asynchronous mode)
ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
EXTMOD 0x1
WAITEN 0x0 (no effect in Asynchronous mode)
WREN As needed
WAITCFG Don't care
Reserved 0x0
WAITPOL Meaningful only if bit 15 is 1
BURSTEN 0x0
Reserved 0x1
FACCEN 0x1
MWID As needed
MTYP 0x02 (NOR Flash memory)
MUXEN 0x0
MBKEN 0x1

Table 138. FMC_BTRx bitfields (mode C)

Bit name
Duration of the data hold phase (DATAHLD HCLK cycles for read
DATAHLD
accesses).
ACCMOD 0x2
DATLAT 0x0
CLKDIV 0x0
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the second access phase (DATAST HCLK cycles) for
DATAST
read accesses.
ADDHLD Don't care
Duration of the first access phase (ADDSET HCLK cycles) for read
ADDSET
accesses. Minimum value for ADDSET is 0.
RM0440 Rev 4
Value to set
Value to set
RM0440