ST STM32G4 Series Reference Manual page 1192

Advanced-control timers (TIM1/TIM8/TIM20)
31 30 29
Res. Res. Res. Res.
15 14 13
OC2
OC2M[2:0]
CE
rw rw rw
Output compare mode:
Bits 31:25 Reserved, must be kept at reset value.
Bits 23:17 Reserved, must be kept at reset value.
Bit 15 OC2CE: Output compare 2 clear enable
Bits 24, 14:12 OC2M[3:0]: Output compare 2 mode
Bit 11 OC2PE: Output compare 2 preload enable
Bit 10 OC2FE: Output compare 2 fast enable
Bits 9:8 CC2S[1:0]: Capture/compare 2 selection
Note: CC2S bits are writable only when the channel is OFF (CC2E = '0' in TIMx_CCER).
Bit 7 OC1CE: Output compare 1 clear enable
1192/2126
28 27 26 25
Res. Res. Res.
12 11 10 9
OC2 OC2
CC2S[1:0]
PE FE
rw rw rw rw
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2
10: CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1
11: CC2 channel is configured as input, tim_ic2 is mapped on tim_trc. This mode is working
only if an internal trigger input is selected through the TS bit (TIMx_SMCR register)
0: tim_oc1ref is not affected by the tim_ocref_clr_int signal
1: tim_oc1ref is cleared as soon as a High level is detected on tim_ocref_clr_int signal
(tim_ocref_clr input or tim_etrf input)
24 23 22
OC2M[3] Res. Res. Res.
rw
8 7 6
OC1
OC1M[2:0]
CE
rw rw rw
RM0440 Rev 4
21 20 19 18
Res. Res. Res.
5 4 3 2
OC1 OC1
PE FE
rw rw rw rw
RM0440
17 16
Res. OC1M[3]
rw
1 0
CC1S[1:0]
rw rw