ST STM32G4 Series Reference Manual page 1211

RM0440
Bit 10 OSSI: Off-state selection for idle mode
This bit is used when MOE=0 due to a break event or by a software write, on channels
configured as outputs.
See OC/OCN enable description for more details
enable register (TIMx_CCER)(x = 1, 8,
0: When inactive, OC/OCN outputs are disabled (the timer releases the output control which
1: When inactive, OC/OCN outputs are first forced with their inactive level then forced to their
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK
Bits 9:8 LOCK[1:0]: Lock configuration
These bits offer a write protection against software errors.
00: LOCK OFF - No bit is write protected.
01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in
Note: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
Bits 7:0 DTG[7:0]: Dead-time generator setup
This bit-field defines the duration of the dead-time inserted between the complementary
outputs. DT correspond to this duration.
DTG[7:5]=0xx => DT=DTG[7:0]x t
DTG[7:5]=10x => DT=(64+DTG[5:0])xt
DTG[7:5]=110 => DT=(32+DTG[4:0])xt
DTG[7:5]=111 => DT=(32+DTG[4:0])xt
Example if T
0 to 15875 ns by 125 ns steps,
16 us to 31750 ns by 250 ns steps,
32 us to 63us by 1 us steps,
64 us to 126 us by 2 us steps
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
28.6.21 TIMx capture/compare register 5 (TIMx_CCR5)(x = 1, 8, 20)
Address offset: 0x048
Reset value: 0x0000 0000
31 30 29
GC5C3 GC5C2 GC5C1 Res.
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15 14 13
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is taken over by the GPIO logic and which imposes a Hi-Z state).
idle level after the deadtime. The timer maintains its control over the output.
bits in TIMx_BDTR register).
register and BKBID/BK2BID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be
written.
register, as long as the related channel is configured in output through the CCxS bits) as
well as OSSR and OSSI bits can no longer be written.
TIMx_CCMRx registers, as long as the related channel is configured in output through
the CCxS bits) can no longer be written.
has been written, their content is frozen until the next reset.
=125ns (8MHz), dead-time possible values are:
DTS
(LOCK bits in TIMx_BDTR register).
28 27 26 25
Res. Res. Res.
12 11 10 9
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Advanced-control timers (TIM1/TIM8/TIM20)
(Section 28.6.11: TIMx capture/compare
20)).
with t =t .
dtg dtg DTS
with T =2xt
dtg dtg
with T =8xt
dtg dtg
with T =16xt
dtg dtg
24 23 22
Res. Res. Res.
8 7 6
CCR5[15:0]
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RM0440 Rev 4
.
DTS
.
DTS
.
DTS
21 20 19 18
Res. Res. CCR5[19:16]
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5 4 3 2
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17 16
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1 0
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