Operation; Operation Of Each Clock; Clock Output Function - NEC V850ES/SA2 UPD703201 Manual

6.4

Operation

6.4.1

Operation of each clock

The following table shows the operation status of each clock.
Main resonator (f )
X
Sub-resonator (f )
XT
CPU clock (f )
CPU
Internal system clock (f )
XX
Peripheral clock (f to f /512)
X X
WDT clock (f )
XW
RTC clock (main)
RTC clock (sub)
Note The watchdog timer clock (f
processor clock control register (PCC) is set to 1.
Remarks CLS bit: Bit 6 of PCC register
MCK bit: Bit 4 of PCC register
√: Operable
×: Stops
<1>: RESET pin input
<2>: During oscillation stabilization time count
<3>: HALT mode
<4>: IDLE mode
<5>: Software STOP mode
<6>: Subclock operation mode
<7>: Sub-IDLE mode
<8>: Backup mode
6.4.2

Clock output function

The clock output function allows the CLKOUT pin to output the internal system clock (f
The internal system clock (f
(PCC).
The CLKOUT pin functions alternately as the PCM1 pin and operates as a clock output pin when the control
register of port CM is manipulated (refer to 4.3.17 Port CM).
The status of the CLKOUT pin is the same as the internal system clock in Table 6-1, and can output the clock when
it is √ (operable). When it is × (stops), it outputs a low level. Immediately after reset <1> and in the operation status of
<2>, the alternate function of the CLKOUT pin is used (PCM1: input mode), and therefore the pin goes into a high-
impedance state.
CHAPTER 6 CLOCK GENERATION FUNCTION
Table 6-1. Operation Status of Each Clock
CLS bit = 0
MCK bit = 0
<1> <2> <3>
× √ √
√ √ √
× × ×
× × √
× × √
× √ √
√ √ √
× √ √
) is operable but it stops operating in the watchdog timer if the CLS bit of the
XW
) is selected by using the CK2 to CK0 bits of the processor clock control register
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Preliminary User's Manual U15905EJ1V0UD
CLS bit = 1
MCK bit = 0
<4> <5> <6> <7>
√ × √
√ √ √
× × √
× × √
× × √
× ×
Note
√ √ √
√ × √
CLS bit = 1
MCK bit = 1
<6> <7> <8>
√ × × ×
√ √ √ √
× √ × ×
× √ × ×
× × × ×
× × × ×
√ √ √ √
√ × × ×
).
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