Configuration Of Watchdog Timer - NEC 78K0R/KE3 User Manual

8.2 Configuration of Watchdog Timer

The watchdog timer includes the following hardware.
Control register
How the counter operation is controlled, overflow time, window open period, and interval interrupt are set by the
option byte.
Setting of Watchdog Timer
Watchdog timer interval interrupt
Window open period
Controlling counter operation of watchdog timer
Overflow time of watchdog timer
Controlling counter operation of watchdog timer
(in HALT/STOP mode)
Remark For the option byte, see CHAPTER 22 OPTION BYTE.
WDTINT of option
byte (000C0H)
(Count value overflow time
WDCS2 to WDCS0 of
option byte (000C0H)
Clock
f
input
IL
controller
WINDOW1 and
WINDOW0 of option
byte (000C0H)
WDTON of option
byte (000C0H)
Remark f : Internal low-speed oscillation clock frequency
IL
290
CHAPTER 8 WATCHDOG TIMER
Table 8-1. Configuration of Watchdog Timer
Item
Watchdog timer enable register (WDTE)
Table 8-2. Setting of Option Bytes and Watchdog Timer
Figure 8-1. Block Diagram of Watchdog Timer
Interval time controller
×
3/4)
10 20
f /2 to f /2
IL IL
20-bit
counter
Count clear
signal
decision signal
Window size check
Watchdog timer enable
register (WDTE)
Internal bus
User's Manual U17854EJ9V0UD
Configuration
Option Byte (000C0H)
Bit 7 (WDTINT)
Bits 6 and 5 (WINDOW1, WINDOW0)
Bit 4 (WDTON)
Bits 3 to 1 (WDCS2 to WDCS0)
Bit 0 (WDSTBYON)
Overflow signal
Selector
Window size
Write detector to
WDTE except ACH
Interval time interrupt
Reset
Internal reset signal
output
controller