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9.2 Configuration of Watchdog Timer
The watchdog timer includes the following hardware.
Control registers
2
Clock
f
/2
R
input
4
f
/2
XP
controller
Watchdog timer enable
register (WDTE)
9.3 Registers Controlling Watchdog Timer
The watchdog timer is controlled by the following two registers.
• Watchdog timer mode register (WDTM)
• Watchdog timer enable register (WDTE)
(1) Watchdog timer mode register (WDTM)
This register sets the overflow time and operation clock of the watchdog timer.
This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be
written only once after reset is released.
RESET input sets this register to 67H.
174
CHAPTER 9 WATCHDOG TIMER
Table 9-3. Configuration of Watchdog Timer
Item
Watchdog timer mode register (WDTM)
Watchdog timer enable register (WDTE)
Figure 9-1. Block Diagram of Watchdog Timer
11
f
/2
to
R
18
f
/2
R
16-bit
counter
or
13
f
/2
to
XP
20
f
/2
XP
2
Clear
0
1
1
WDCS4
Watchdog timer mode
register (WDTM)
Internal bus
Preliminary User's Manual U16846EJ1V0UD
Configuration
Output
Selector
controller
3
3
WDCS3
WDCS2
WDCS1 WDCS0
Internal reset signal
Option byte
(to set "Ring-OSC
cannot be stopped" or
"Ring-OSC can be
stopped by software")
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