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System Design Considerations
Figure 7-4. S0-S3-S0 Transition
Stop Grant Cycle
Go_C3 from ICH
Ack_C3 from GMCH
Cycle 1 from GMCH
Cycle 1 from ICH
Cycle 2 from GMCH
Cycle 2 from ICH
7-10
Vcc3.3sus
RSMRST#
STPCLK#
t18
CPUSLP#
DRAM
DRAM ac
t19
SUS_STAT#
PCIRST#
CPURST#
SLP_S3#
SLP_S5#
PWROK
Vcc3.3core
Clocks
Clocks valid
Freq straps
Wake Event
t7
DRAM in STR (CKE low)
t20
t21
t23
t8
t22
Clocks invalid
t24
DRAM active
t11
t12
t13
t17
t9
Clocks valid
t15
t16
®
Intel
810A3 Chipset Design Guide
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