Intel 810A3 Design Manual page 7

4-35
4-36
4-37
4-38
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
6-1
6-2
6-3
7-1
7-2
7-3
7-4
7-5
8-1
8-2
®
Intel 810A3 Chipset Design Guide
RAMDAC Component and Routing Guidelines ..........................................4-34
Recommended RAMDAC Reference Resistor Placement and
Connections ................................................................................................4-35
Recommended LC Filter Connection..........................................................4-36
Frequency Response (see
PICD[1,0] Uni-Processor Topology...............................................................5-7
Test Load vs. Actual System Load ...............................................................5-9
Aggressor and Victim Networks..................................................................5-11
Transmission Line Geometry: (A) Microstrip (B) Stripline...........................5-11
One Signal Layer and One Reference Plane..............................................5-15
Layer Switch with One Reference Plane ....................................................5-15
Layer Switch with Multiple Reference Planes (same type) .........................5-15
Layer Switch with Multiple Reference Planes .............................................5-16
One Layer with Multiple Reference Planes.................................................5-16
Overdrive Region and V
Rising Edge Flight Time Measurement.......................................................5-19
®
Intel 810A3 Chipset Clock Architecture ......................................................6-2
Different Topologies for the Clock Routing Guidelines .................................6-5
Example of Capacitor Placement Near Clock Input Receiver.......................6-6
®
Intel 810A3 Chipset Power Delivery Architecture .......................................7-2
82810A3 GMCH Power Plane Decoupling ...................................................7-8
G3-S0 Transistion .........................................................................................7-9
S0-S3-S0 Transition....................................................................................7-10
S0-S5-S0 Transition....................................................................................7-11
Pullup Resistor Example.............................................................................8-15
PWRGOOD and PWROK Logic .................................................................8-17
Table 4-13).......................................................4-38
Guardband.....................................................5-19
REF
vii