Intel 810A3 Design Manual page 18

Introduction
Term
Suspend-To-RAM
(STR)
Test Load
Trunk
Undershoot
Victim
V Guardband
REF
1-6
Definition
In the STR state, the system state is stored in main memory and all
unnecessary system logic is turned off. Only main memory and logic
required to wake the system remain powered.
Intel uses a 50 Ω test load for specifying its components.
The main connection, excluding interconnect branches, terminating at
agent pads.
Maximum voltage allowed for a signal to extend below V
processor core pad. See the respective Processor's Electrical,
Mechanical, and Thermal Specification for undershoot specifications.
A network that receives a coupled cross-talk signal from another
network is called the victim network.
A guardband (DV ) defined above and below V
REF
realistic model accounting for noise such as cross-talk, V
V noise.
REF
at the
SS
to provide a more
REF
noise, and
TT
®
Intel 810A3 Chipset Design Guide