Theory; Agtl; Timing Requirements - Intel 810A3 Design Manual

Advanced System Bus Design
5.2

Theory

5.2.1

AGTL+

AGTL+ is the electrical bus technology used for the processor bus. This is an incident wave
switching, open-drain bus with external pull-up resistors that provide both the high logic level and
termination at each load. The processor AGTL+ drivers contain a full-cycle active pull-up device
to improve system timings. The AGTL+ specification defines:
•
Termination voltage (V
•
Receiver reference voltage (V
•
processor termination resistance (R
•
Input low voltage (V
•
Input high voltage (V
•
NMOS on resistance (R
•
PMOS on resistance (R
•
Edge rate specifications.
•
Ringback specifications.
•
Overshoot/Undershoot specifications.
•
Settling Limit.
5.2.2

Timing Requirements

The system timing for AGTL+ is dependent on many things. Each of the following elements
combine to determine the maximum and minimum frequency the AGTL+ bus can support:
•
The range of timings for each of the agents in the system.
— Clock to output [T
"specification" load therefore the T
T
— The minimum required setup time to clock [T
•
The range of flight time between each component. This includes:
— The velocity of propagation for the loaded printed circuit board [S
— The board loading impact on the effective T
•
The amount of skew and jitter in the system clock generation and distribution.
•
Changes in flight time due to cross-talk, noise, and other effects.
5-10
).
TT
REF
).
IL
).
IH
).
ON N
).
ON P
]. (Note that the system load is likely to be different from the
CO
from the specification.)
CO
) as a function of termination voltage (V
).
TT
observed in the system might not be the same as the
CO
] for each receiving agent.
SU_MIN
in the system.
CO
Intel
).
TT
].
EFF
®
810A3 Chipset Design Guide