Intel 810A3 Design Manual page 8

Tables
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
3-1
3-2
3-3
3-4
3-5
3-6
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
5-1
5-2
6-1
6-2
6-3
6-4
7-1
7-2
7-3
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
viii
Platform Pin Definition Comparison for Single Processor Designs ..............2-2
Processor Pin Definition Comparison ...........................................................2-3
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Intel Pentium III Processor and GMCH AGTL+ Parameters for
Example Calculations ...................................................................................2-4
Example T Calculations FOR 100 MHz Bus .....................................2-5
FLT_MIN
Example T Calculations (Frequency Independent)...........................2-5
FLT_MIN
Segment Descriptions and Lengths for
Trace Width (Space Guidelines)...................................................................2-6
Routing Guidelines for Non-AGTL+ Signals .................................................2-8
Example Resistor Values for CLKREF Divider Circuit (3.3V Source).........2-10
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Intel Pentium III Processor and GMCH AGTL+ Parameters for
Example Calculations ...................................................................................3-1
Example T Calculations for 100 MHz Bus .......................................3-2
FLT_MAX
Example T Calculations (Frequency Independent)...........................3-2
FLT_MIN
Segment Descriptions and Lengths for
Trace Width:Space Guidelines .....................................................................3-3
Routing Guidelines for Non-AGTL+ Signals .................................................3-4
System Memory Routing ..............................................................................4-5
Display Cache Routing (Topology 1) ............................................................4-8
Display Cache Routing (Topology 2) ............................................................4-8
Display Cache Routing (Topology 3) ............................................................4-8
Display Cache Routing (Topology 4) ............................................................4-9
AC'97 Configuration Combinations.............................................................4-18
Recommended USB Trace Characteristics ................................................4-23
Inductor.......................................................................................................4-30
Capacitor ....................................................................................................4-30
Resistor.......................................................................................................4-30
DPLL LC Filter Component Example..........................................................4-37
Additional DPLL LC Filter Component Example.........................................4-38
Resistance Values for Frequency Response Curves (see
Trace Width Space Guidelines .....................................................................5-6
Host Clock Routing .......................................................................................5-6
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Intel 810A3 Chipset Clocks.........................................................................6-1
Group Skew and Jitter Limits at the Pins of the Clock Chip .........................6-3
Signal Group and Resistor............................................................................6-3
Layout Dimensions .......................................................................................6-4
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Intel 810A3 Chipset Power Map .................................................................7-3
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Intel 810A3 Chipset Voltage Regulator Specifications ...............................7-4
Power Sequencing Timing Definitions ........................................................7-12
AGTL+ Connectivity Checklist for 370-Pin Socket Processors.....................8-2
CMOS Connectivity Checklist for 370-Pin Socket Processors .....................8-3
TAP Checklist for a 370-Pin Socket Processor ...........................................8-3
Miscellaneous Checklist for 370-Pin Socket Processors ..............................8-4
AGTL+ Connectivity Checklist for SC242 Processors ..................................8-5
CMOS Connectivity Checklist for SC242 Processors...................................8-6
TAP Checklist for SC242 Processors ...........................................................8-6
Miscellaneous Checklist for SC242 Processors ...........................................8-6
Special Consideration Checklist ...................................................................8-7
Clock Generator Checklist ............................................................................8-7
Figure 2-1 .......................................2-6
Figure 3-2 ......................................3-3
Figure
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Intel 810A3 Chipset Design Guide
4-38).....4-39