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ATX Power Supply PWRGOOD Signal Glitches. The PWROK signal must be glitch free for
proper power management operation. The ICH sets the PWROK_FLR bit (ICH
GEN_PMCON_2, General PM Configuration 2 Register, PM-dev31: function 0, bit 0, at
Offset A2h). If this bit is set upon resume from S3 power down, the system will reboot, and
control of the system will not be given to the program running when entering the S3 state.
System designers should insure that PWROK signal designs are glitch free. Intel has observed
anomalies on ATX PWRGOOD signals that cause glitches on PWROK signals. Populating
C183 with a 1.0 uF capacitor on the Intel
PWROK glitching. System designers should insure that their designs provide glitch free
operation on the PWROK signal.
•
PWRGOOD signal to CPU is driven with an open collector buffer pulled up to 2.5V using a
330 ohm resistor.
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The circuitry checks for both processor VRM powered up, and the PS_POK signal from the
ATX power supply connector before asserting PWRGOOD and PWROK to the processor and
ICH.
Figure 8-2. PWRGOOD and PWROK Logic
V R M _ P W R G D
I T P _ R E S E T
A T X _ P S _ P O K
Note: The polarities have been altered to simplify drawing.
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RI# can be connected to the serial port if this feature is used. To implement ring indicate as a
wake event, the RS232 transceiver driving the RI# signal must be powered when the ICH
suspend well is powered. This can be achieved with a serial port transceiver powered from the
standby well that implements a shutdown feature.
•
SLP_S3# from the ICH must be inverted and then connected to PSON of the power supply
connector to control the state of the core well during sleep states.
•
For an ATX power supply, when PSON is low, the core wells are turned on. When PSON is
high, the core wells from the power supply are turned off.
®
Intel
810A3 Chipset Design Guide
®
810A3 chipset reference schematics eliminated
Simplified PWRGOOD and PWROK
generation logic
V C C
Design Checklist
P W R G O O D t o
Processor (2.5V)
PWROK to ICH (3.3V)
pwrgood.vsd
8-17
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