Intel 810A3 Design Manual page 5

5.3
5.4
5.5
6 Clocking .....................................................................................................................6-1
6.1
6.2
6.3
6.4
6.5
7 System Design Considerations..................................................................................7-1
7.1
7.2
7.3
7.4
8 Design Checklist ........................................................................................................8-1
8.1
8.2
8.3
8.4
9 Third-Party Vendor Information..................................................................................9-1
A PCI Devices/Functions/Registers/Interrupts ............................................................. A-1
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Intel 810A3 Chipset Design Guide
5.2.2 Timing Requirements.....................................................................5-10
5.2.3 Cross-Talk Theory .........................................................................5-11
More Details and Insight .............................................................................5-13
5.3.1 Textbook Timing Equations ...........................................................5-13
5.3.2 Effective Impedance and Tolerance/Variation ...............................5-14
5.3.3 Power/Reference Planes, PCB Stackup, and High
Frequency Decoupling ...................................................................5-14
5.3.4 Clock Routing.................................................................................5-17
Definitions of Flight Time Measurements/Corrections and Signal Quality ..5-18
5.4.1 V Guardband............................................................................5-18
REF
5.4.2 Ringback Levels.............................................................................5-18
5.4.3 Overdrive Region ...........................................................................5-18
5.4.4 Flight Time Definition and Measurement .......................................5-19
Conclusion ..................................................................................................5-19
Clock Generation ..........................................................................................6-1
Clock Architecture.........................................................................................6-2
Clock Routing Guidelines..............................................................................6-3
Capacitor Sites..............................................................................................6-6
Clock Power Decoupling Guidelines.............................................................6-6
Power Delivery..............................................................................................7-1
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7.1.1 Intel 810A3 Chipset Power Delivery ..............................................7-1
7.1.2 LED Indicator for S0-S5 States........................................................7-5
Decoupling Guidelines ..................................................................................7-6
7.2.1 Vcc Decoupling........................................................................7-6
CORE
7.2.2 Phase Lock Loop (PLL) Decoupling ................................................7-6
7.2.3 82810A3 GMCH Decoupling Guidelines..........................................7-7
7.2.4 Ground Flood Planes........................................................................7-8
Thermal Design Power .................................................................................7-8
Power Sequencing........................................................................................7-9
Design Review Checklist ..............................................................................8-1
8.1.1 Design Checklist Summary ..............................................................8-1
Pullup and Pulldown Resistor Values .........................................................8-15
RTC.............................................................................................................8-16
Power Management Signals .......................................................................8-16
8.4.1 Power Button Implementation........................................................8-18
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