Intel ® 810A3 Chipset Power Delivery Architecture - Intel 810A3 Design Manual

System Design Considerations

Figure 7-1. Intel 810A3 Chipset Power Delivery Architecture
®
Intel 810A3 Chipset
Platform Power Map
5 V S B
± 5 % ± 5 %
5V Dual
Switch
NOTE: The above current values represent the maximum sustained current draw.
7-2
ATX P/S
with 720mA 5VSB
5 V 3.3V 12V
-12V
± 5 % ± 5 % ± 1 0 %
VTT Regulator
2.5V Regulator
1.8V Regulator
3.3VSB Regulator
AC'97 12V: 12V ±0.6V
500mA S0, S1
AC'97 -12V: -12V ±1.2V
100mA S0, S1
AC'97 5V: 5V ±0.25V
1.00A S0,S1
AC'97 5VSB: 5VSB ±0.25V
500mA S0, S1
AC'97 3.3V: 3.3V ±0.165V
1.00A S0,S1
AC'97 3.3VSB: 3.3VSB ±0.165V
150mA S3, S5
USB Cable Power: 5V ±0.25V
1A S0, S1
-Shaded regulators/components are on in S3, S5
-KB/Mouse will not support STR
-Total Max Power Dissipation for GMCH = 4W
-Total Max Power Dissipation for AC'97 = 15W
Processor
Core: VCC_VID: 1.65V
17.2A S0, S1
V R M
Core: VCC_VID: 2.0V
Core: VCC_VID: 2.0V
15.6A S0, S1
17.8A S0, S1
VTT: 1.5V ±0.135V
2.7A S0, S1
VCC3: 3V ±0.165V
15 mA S0, S1
CK810-2.5: 2.5V ±0.125V
100mA S0, S1
CK810-3.3: 3.3V ±0.165V
280mA S0, S1
®
Intel 810E Chipset
GMCH Core: 1.8V ±0.09V
1.40A S0, S1
GMCH: 3.3V ±0.165V
1.40A S0, S1
GMCH: 3.3VSB ±0.165V
110mA S3, S5
ICH Hub I/O: 1.8V ±0.09V
55mA S0, S1
AC'97
ICH Core: 3.3V ±0.3V
300mA S0, S1
ICH Resume: 3.3VSB ±0.3V
1.5mA S0, S1; 300uA S3, S5
ICH RTC: 3.3VSB ±0.3V
5uA S0, S1, S3, S5
FWH Flash BIOS Core:
3.3V ±0.3V
67mA S0, S1
F A N
Serial Ports
Serial Xceivers-12: 12V ±1.2V
22mA S0, S1
Serial Xceivers-N12: -12V ±1.2V
28mA S0, S1
Serial Xceivers-5: 5V ±0.25V
30mA S0, S1
Display Cache: 3.3V ±0.3V
960mA S0, S1
C L K
Super I/O
LPC Super I/O: 3.3V ±0.3V
50mA S0, S1
PS/2 Keyboard/Mouse 5V ±0.5V
1A S0, S1
2 DIMM Slots: 3.3VSB ±0.3V
4.8A S0, S1; 64mA S3
82559 LAN Down 3.3VSB ±0.3V
195mA S0,S1; 120mA S3, S5
(3) PCI 3.3Vaux: 3.3VSB ±0.3V
1.125A S0, S1; 60mA S3, S5
®
Intel 810A3 Chipset Design Guide
-12V
PCI