Intel 810A3 Design Manual page 16

Introduction
Term
Flight Time
Full-power operation
GTL+
Network
Network Length
1-4
Definition
Flight Time is a term in the timing equation that includes the signal
propagation delay, any effects the system has on the T
plus any adjustments to the signal at the receiver needed to guarantee the
setup time of the receiver.
More precisely, flight time is defined to be:
•
The time difference between a signal at the input pin of a receiving
agent crossing V
REF
conditions required for AC timing specifications; i.e., ringback,
etc.), and the output pin of the driving agent crossing V
driver was driving the Test Load used to specify the driver's AC
timings.
See Section for details regarding flight time simulation and
validation.
The V Guardband takes into account sources of noise that may
REF
affect the way an AGTL+ signal becomes valid at the receiver. See
the definition of the V
•
Maximum and Minimum Flight Time - Flight time variations can
be caused by many different parameters. The more obvious causes
include variation of the board dielectric constant, changes in load
condition, cross-talk, V
termination resistance and differences in I/O buffer performance as
a function of temperature, voltage and manufacturing process.
Some less obvious causes include effects of Simultaneous
Switching Output (SSO) and packaging effects.
•
The Maximum Flight Time is the largest flight time a network will
experience under all variations of conditions. Maximum flight time
is measured at the appropriate V
•
The Minimum Flight Time is the smallest flight time a network
will experience under all variations of conditions. Minimum flight
time is measured at the appropriate V
For more information on flight time and the V
Pentium II Processor Developer's Manual.
®
During full-power operation, all components on the motherboard remain
powered. Note that full-power operation includes both the full-on
operating state (S0) and the processor Stop Grant state (S1).
GTL+ is the bus technology used by the Pentium Pro processor. This is
an incident wave switching, open-drain bus with pull-up resistors that
provide both the high logic level and termination. It is an enhancement
to the GTL (Gunning Transceiver Logic) technology. See the Pentium
II Processor Developer's Manual for more details of GTL+.
The trace of a Printed Circuit Board (PCB) that completes an electrical
connection between two or more components.
The distance between extreme bus agents on the network and does not
include the distance connecting the end bus agents to the termination
resistors.
(adjusted to meet the receiver manufacturer's
Guardband.
REF
noise, V noise, variation in
TT REF
Guardband boundary.
REF
Guardband boundary.
REF
Guardband, see the
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®
Intel 810A3 Chipset Design Guide
of the driver,
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if the
REF
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