Validation - Intel 810A3 Design Manual

Advanced System Bus Design
AGTL+ Cross-talk simulation involves the following cases:
•
Intra-group AGTL+ cross-talk
•
Inter-group AGTL+ cross-talk
•
Non-AGTL+ to AGTL+ cross-talk
5.1.5.3 Monte Carlo Analysis
Perform a Monte Carlo analysis on the extracted baseboard. Vary all parameters recommended for
the pre-layout Monte Carlo analysis within the region that they are expected to vary. The range for
some parameters will be reduced compared to the pre-layout simulations. For example, baseboard
lengths L1 through L7 should no longer vary across the full min and max range on the final
baseboard design. Instead, baseboard lengths should now have an actual route, with a length
tolerance specified by the baseboard fabrication manufacturer.
5.1.6

Validation

Build systems and validate the design and simulation assumptions.
5.1.6.1 Measurements
Note that the AGTL+ specification for signal quality is at the pad of the component. The expected
method of determining the signal quality is to run analog simulations for the pin and the pad. Then
correlate the simulations at the pin against actual system measurements at the pin. Good correlation
at the pin leads to confidence that the simulation at the pad is accurate. Controlling the temperature
and voltage to correspond to the I/O buffer model extremes should enhance the correlation between
simulations and the actual system.
5.1.6.2 Flight Time Simulation
As defined in
difference between a signal crossing V
driver crossing V
in this guideline assume the actual system load is 50 Ω and is equal to the test load. While the DC
loading of the AGTL+ bus in a DP mode is closer to 25 Ω, AC loading is approximately 29 Ω since
the driver effectively "sees" a 56 Ω termination resistor in parallel with a 60 Ω transmission line on
the cartridge.
5-8
Section 1.1.1, "Terminology and Definitions" on page
REF
were it driving a test load. The timings in the tables and topologies discussed
REF
at the input pin of the receiver, and the output pin of the
®
Intel
1-2, flight time is the time
810A3 Chipset Design Guide