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Design Checklist
Table 8-4. Miscellaneous Checklist for 370-Pin Socket Processors
CPU Pin
BCLK
BSEL0
BSEL1
CLKREF
CPUPRES#
EDGCTRL
PICCLK
PLL1, PLL2
RTTCTRL
(S35)
SLEWCTRL
(E27)
THERMDN
THERMDP
VCC_1.5
VCC_2.5
VCC
CMOS
VCC
CORE
VCORE
DET
(E21)
VID[3:0]
VID[4]
VREF[7:0]
8-4
I/O
Connect to clock generator / 22-33 Ω series resistor (though OEM needs to
I
simulate based on driver characteristics). To reduce pin-to-pin skew, tie host clock
outputs together at the clock driver then route to the GMCH and processor.
Case 1, 66/100 MHz support: 1 KΩ pullup resistor to 3.3V, connect to CK810
SEL0 input, connect to GMCH LMD29 pin via 10 KΩ series resistor.
I/O
Case 2, 100 MHz support: 1 KΩ pullup resistor to 3.3V, connect to PWRGOOD
logic such that a logic low on BSEL0 negates PWRGOOD.
1 KΩ pullup resistor to 3.3V, connect to CK810 REF pin via 10 KΩ series resistor,
I/O
connect to GMCH LMD13 pin via 10 KΩ series resistor.
Connect to divider on VCC_2.5 or VCC_3.3 to create 1.25V reference with a
I
4.7 uF decoupling capacitor. Resistor divider must be created from 1% tolerance
resistors. Do not use VTT as source voltage for this reference!
Tie to ground, leave as No Connect, or could be connected to PWRGOOD logic to
gate system from powering on if no processor is present. If used, 1 KΩ–10 KΩ
pullup resistor to any voltage.
51 Ω ±5% pullup resistor to VCC
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Connect to clock generator / 22–33 Ω series resistor (though OEM needs to
I
simulate based on driver characteristics).
Low pass filter on VCC
I
in series with VCC
capacitor to PLL2.
5
110 Ω ±1% pulldown resistor to ground.
110 Ω ±1% pulldown resistor to ground.
No Connect if not used; otherwise connect to thermal sensor using vendor
O
guidelines.
No Connect if not used; otherwise connect to thermal sensor using vendor
I
guidelines.
Connected to same voltage source as V
I
frequency decoupling.
Connected to 2.5V voltage source. Should have some high and low frequency
I
decoupling.
Used as pull-up voltage source for CMOS signals between processor and chipset
O
and for TAP signals between processor and ITP. Must have some decoupling (HF/
LF) present.
10 ea (min) 4.7 uF in 1206 package all placed within the PGA370 socket cavity.
I
8 ea (min) 1 uF in 0612 package placed in the PGA370 socket cavity.
220 Ω pullup resistor to 3.3V, connect to GMCH LMD27 pin via 10 KΩ series
O
resistor.
Connect to on-board VR or VRM. For on-board VR, 10 KΩ pullup resistor to
power-solution compatible voltage required (usually pulled up to input voltage of
O
the VR). Some of these solutions have internal pullups. Optional override
(jumpers, ASIC, etc.) could be used. May also connect to system monitoring
device.
N/A
Connect regulator controller pin to ground (not on processor).
Connect to Vref voltage divider made up of 75 and 150 ohm 1% resistors
connected to Vtt.
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Decoupling Guidelines:
4 ea. (min) 0.1 uF in 0603 package placed within 500 mils of VREF pins.
Comments
.
CORE
provided on motherboard. Typically a 4.7 uH inductor
CORE
is connected to PLL1 then through a series 33 uF
CORE
. Must have some high and low
TT
Intel
®
810A3 Chipset Design Guide
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