Calculations For 100 Mhz Bus - Intel 810A3 Design Manual

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Table 2-4

minimum flight time calculation for a 100 MHz processor system using the Intel

processor/Intel

jitter were used. Clock skew and clock jitter values are dependent on the clock components

and distribution method chosen for a particular design and must be budgeted into the initial

timing equations as appropriate for each design.

Table 2-4

•

CLK

two host clock outputs together ("ganging") at clock driver output pins, and the PCB clock

routing skew is 150 ps. System timing budget must assume 0.175 ns of clock driver skew if

outputs are not tied together and a clock driver that meets the CK810 Clock Synthesizer/Driver

Specification is being used.)

•

CLK

See the appropriate Intel

Specification for details on clock skew and jitter specifications. Exact details of host clock routing

topology are provided with the platform design guideline.

Table 2-4. Example T

Driver

Processor

GMCH

NOTES:

1. All times in nanoseconds.

2. BCLK period = 10 ns @ 100 MHz.

3. The flight times in this column include margin to account for the following phenomena that Intel has observed

when multiple bits are switching simultaneously. These multi-bit effects can adversely affect flight time and

signal quality and are sometimes not accounted for in simulation. Accordingly, maximum flight times depend

on the baseboard design and additional adjustment factors or margins are recommended.

•

SSO push-out or pull-in.

•

Rising or falling edge rate degradation at the receiver caused by inductance in the current return path,

requiring extrapolation that causes additional delay.

•

Cross-talk on the PCB and internal to the package can cause variation in the signals.

There are additional effects that may not necessarily be covered by the multi-bit adjustment factor and

should be budgeted as appropriate to the baseboard design. Examples include:

•

The effective board propagation constant (S

— Dielectric constant (ε

— The type of trace connecting the components (stripline or microstrip).

— The length of the trace and the load of the components on the trace. Note that the board propagation

constant multiplied by the trace length is a component of the flight time but not necessarily equal to

the flight time.

Table 2-5. Example T

Driver

Processor

GMCH

NOTES:

1. All times in nanoseconds.

Intel

810A3 Chipset Design Guide

gives an example AGTL+ initial maximum flight time and



810A3 chipset system bus. Note that assumed values for clock skew and clock

and

Table 2-5

are derived assuming:

= 0.20 ns (Note: Assumes clock driver pin-to-pin skew is reduced to 50 ps by tying

SKEW

= 0.250 ns

JITTER



810A3 chipset documentation, and CK810 Clock Synthesizer/Driver