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5.1.4.4
APIC Data Bus Routing
Intel recommends using the in-line topology shown in
PICD[1:0].
Figure 5-1. PICD[1,0] Uni-Processor Topology
5.1.5
Post-Layout Simulation
Following layout, extract the interconnect information for the board from the CAD layout tools.
Run simulations to verify that the layout meets timing and noise requirements. A small amount of
"tuning" may be required; experience at Intel has shown that sensitivity analysis dramatically
reduces the amount of tuning required. The post layout simulations should take into account the
expected variation for all interconnect parameters.
Intel specifies signal integrity at the device pads and therefore recommends running simulations at
the device pads for signal quality. However, Intel specifies core timings at the device pins, so
simulation results at the device pins should be used later to correlate simulation performance
against actual system measurements.
5.1.5.1
Intersymbol Interference
Intersymbol Interference (ISI) refers to the distortion or change in the waveform shape caused by
the voltage and transient energy on the network when the driver begins its next transition.
Intersymbol Interference (ISI) occurs when transitions in the current cycle interfere with transitions
in subsequent cycles. ISI can occur when the line is driven high, low, and then high in consecutive
cycles (the opposite case is also valid). When the driver drives high on the first cycle and low on
the second cycle, the signal may not settle to the minimum V
This results in improved flight times in the third cycle. Intel performed ISI simulations for the
topology given in this section by comparing flight times for the first and third cycle. ISI effects do
not necessarily span only 3 cycles so it may be necessary to simulate beyond 3 cycles for certain
designs. After simulating and quantifying ISI effects, adjust the timing budget accordingly to take
these conditions into consideration.
5.1.5.2
Cross-Talk Analysis
AGTL+ cross-talk simulations can consider the processor core package, GMCH package, and
SC242 connectors as non-coupled. Treat the traces on the processor cartridge and baseboard as
fully coupled for maximum cross-talk conditions. Simulate the traces as lossless for worst case
cross-talk and lossy where more accuracy is needed. Evaluate both odd and even mode cross-talk
conditions.
®
Intel
810A3 Chipset Design Guide
2.5V
®
Intel
820
Chipset
Z0=60 Ω ±15%.
L(1):
Advanced System Bus Design
Figure 5-1
for the APIC Data signals,
S C 2 4 2
150 Ω
L1 < 8"
PICD[1,0]
before the next rising edge is driven.
OL
5-7
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