Clock Architecture - Intel 810A3 Design Manual

Clocking
6.2

Clock Architecture


Figure 6-1. Intel 810A3 Chipset Clock Architecture
2.5V
Clock Synthesizer
6-2
52
CPU_2_ITP
55
APIC_0
50
CPU_1
49
CPU_0
32
P W R D W N
29
SEL1
28
SEL0
30
S D A T A
31
SCLK
46
S D R A M 0
45
S D R A M 1
43
S D R A M 2
42
S D R A M 3
40
S D R A M 4
39
S D R A M 5
37
S D R A M 6
36
S D R A M 7
34
3.3V
D C L K
7
3V66_0
25
USB_0
14.3118 MHz
8
3V66_1
1
R E F
11
PCIO/ICH
26
USB1
54
2.5V
APIC1
12
PCI_1
13
PCI_2
3.3V
15
PCI_3
16
PCI_4
18
PCI_5
19
PCI_6
20
PCI_7
ITP
Data
Main Memory
2 DIMMS
Address
Control
Dot Clock
Processor
G M C H
ICH/ICH0
32.768 KHz
SIO
PCI Total of 6 devices
(µATX)
(5 slots + 1 down)
clk_arch.vsd
®
Intel 810A3 Chipset Design Guide