Table of Contents
Advertisement
Figure 7-5. S0-S5-S0 Transition
Stop Grant Cycle
Go_C3 from ICH
Ack_C3 from GMCH
Cycle 1 from GMCH
Cycle 1 from ICH
Cycle 2 from GMCH
Cycle 2 from ICH
®
Intel
810A3 Chipset Design Guide
Vcc3.3sus
RSMRST#
STPCLK#
t18
CPUSLP#
DRAM
DRAM ac
t19
SUS_STAT#
t20
PCIRST#
CPURST#
SLP_S3#
SLP_S5#
PWROK
Vcc3.3core
Clocks
Clocks valid
Freq straps
Wake Event
System Design Considerations
t7
DRAM in STR (CKE low)
t11
t21
t23
t25
t26
t8
t22
t9
Clocks invalid
t24
DRAM active
t12
t13
t17
Clocks valid
t15
t16
7-11
Advertisement
Table of Contents
