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Layout and Routing Guidelines
4.14.4
Recommendation for Intel Platforms
The following tables are examples of components that meet Intel's recommendations, when
configured in the topology presented in
Table 4-8. Inductor
TDK MLF2012A4R7KT
Murata LQG21N4R7K00T1
Murata LQG21C4R7N00
Table 4-9. Capacitor
Kemet T495D336M016AS
AVX TPSD336M020S0200
Table 4-10. Resistor
Value
1 Ω
To satisfy damping requirements, total series resistance in the filter (from V
the capacitor) must be at least 0.35 Ω. This resistor can be in the form of a discrete component, or
routing, or both. For example, if the picked inductor has a minimum DCR of 0.25 Ω, then a routing
resistance of at least 0.10 Ω is required. Be careful not to exceed the maximum resistance rule
(2 Ω). For example, if using discrete R1, the maximum DCR of the L should be less than
2.0 - 1.1 = 0.9 Ω, which precludes using some inductors.
Other routing requirements:
C should be close to PLL1 and PLL2 pins, < 0.1 Ω per route. These routes do not count
•
towards the minimum damping R requirement.
•
PLL2 route should be parallel and next to PLL1 route (minimize loop area).
•
L should be close to C; any routing resistance should be inserted between V
•
Any discrete R should be inserted between V
Figure 4-31. Using Discrete R
4-30
Part Number
Part Number
Tolerance
Power
10%
1/16 W
VCC
C O R E
R
Discrete Resistor
Figure
4-29.
Value
Tol
SRF
4.7 uH
10%
35 MHz
4.7 uH
10%
47 MHz
4.7 uH
30%
35 MHz
Value
Tolerance
33 uF
20%
33 uF
20%
Resistor may be implemented with trace resistance, in which
discrete R is not needed
and L.
CC
CORE
L
<0.1 ohm route
C
<0.1 ohm route
Rated I
DCR
0.56 Ω (1W max)
30 mA
0.7 Ω (±50%)
30 mA
30 mA
0.3Ω max
ESL
ESR
0.225 Ω
2.5 nH
0.2 Ω
TBD
Note
to the top plate of
CC
CORE
and L.
CC
CORE
PLL1
370-Pin
Socket
PLL2
®
Intel
810A3 Chipset Design Guide
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