Calculations For 100 Mhz Bus - Intel 810A3 Design Manual

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SC242 Processor Design Guidelines

Table 3-2

•

CLK

two host clock outputs together ("ganging") at clock driver output pins, and the PCB clock

routing skew is 150 ps. System timing budget must assume 0.175 ns of clock driver skew if

outputs are not tied together and a clock driver that meets the CK810 clock driver specification

is being used.)

•

CLK

Some clock driver components may not support ganging the outputs together. Be sure to

verify with your clock component vendor before ganging the outputs. See the respective

processor's Electrical, Mechanical, and Thermal Specification, appropriate Intel

documentation, and CK810 Clock Synthesizer/Driver Specification for details on clock skew and

jitter specifications.

Table 3-2. Example T

Driver

Processor

GMCH

NOTES:

1. All times in nanoseconds.

2. BCLK period = 10 ns @ 100 MHz.

3. The flight times in this column include margin to account for the following phenomena that Intel has observed

when multiple bits are switching simultaneously. These multi-bit effects can adversely affect flight time and

signal quality and are sometimes not accounted for in simulation. Accordingly, maximum flight times depend

on the baseboard design and additional adjustment factors or margins are recommended.

•

SO push-out or pull-in.

•

Rising or falling edge rate degradation at the receiver caused by inductance in the current return path,

requiring extrapolation that causes additional delay.

•

Cross-talk on the PCB and internal to the package can cause variation in the signals.

There are additional effects that may not necessarily be covered by the multi-bit adjustment factor and

should be budgeted as appropriate to the baseboard design. Examples include:

•

The effective board propagation constant (S

— Dielectric constant (ε

— The type of trace connecting the components (stripline or microstrip).

— The length of the trace and the load of the components on the trace. Note that the board propagation

constant multiplied by the trace length is a component of the flight time but not necessarily equal to

the flight time.

Table 3-3. Example T

Driver

Processor

GMCH

NOTES:

1. All times in nanoseconds.

3-2

and

Table 3-3

are derived assuming:

= 0.2 ns (Note: Assumes clock driver pin-to-pin skew is reduced to 50 ps by tying

SKEW

= 0.250 ns

JITTER