Clock Routing - Intel 810A3 Design Manual

5.3.3.4 SC242 Connector
Intel studies indicate that the use of thermal reliefs on the connector pin layout pattern (especially
ground pins) should be minimized. Such reliefs (cartwheels or wagon-wheels) increase the net
ground inductance and reduce the integrity of the ground plane to which many signals are
referenced. Increased ground inductance has been shown to aggravate SSO effects. Also, the anti-
pad diameters (clearance holes in the planes) for the signal pins should be minimized since large
anti-pads also reduce the integrity of the ground plane and increase inductance.
Some additional layout and EMI-reduction guidelines regarding the SC242 connector follow:
•
Extend power/ground planes up to the SC242 connector pins.
•
Extend the reference planes for AGTL+ and other controlled-impedance signals up to the
SC242 connector pins.
•
Minimize or remove thermal reliefs on power/ground pins.
•
Route V
across V
•
Use a ground plane under the principal component side of the baseboard (and secondary side if
it contains active components).
•
Distribute decoupling capacitors across power and ground pins evenly around the connector
(less than 0.5 inch spacing) on the primary and secondary sides.
•
Minimize serpentine traces on outer layers.
5.3.4

Clock Routing

Analog simulations are required to ensure clock net signal quality and skew is acceptable. The
system clock skew must be kept to a minimum (The calculations and simulations for the example
topology given in this document have a total clock skew of 200 ps and 150 ps of clock jitter). For a
given design, the clock distribution system, including the clock components, must be evaluated to
ensure these same values are valid assumptions. Each processor's datasheet specifies the clock
signal quality requirements. To help meet these specifications, follow these general guidelines:
•
Tie clock driver outputs if clock buffer supports this mode of operation.
•
Match the electrical length and type of traces on the PCB (microstrip and stripline may have
different propagation velocities).
•
Maintain consistent impedance for the clock traces.
— Minimize the number of vias in each trace.
— Minimize the number of different trace layers used to route the clocks.
— Keep other traces away from clock traces.
•
Lump the loads at the end of the trace if multiple components are to be supported by a single
clock output.
•
Have equal loads at the end of each network.
The ideal way to route each clock trace is on the same single inner layer, next to a ground plane,
isolated from other traces, with the same total trace length, to the same type of single load, with an
equal length ground trace parallel to it, and driven by a zero skew clock driver. When deviations
from ideal are required, going from a single layer to a pair of layers adjacent to power/ground
planes would be a good compromise. The fewer number of layers the clocks are routed on, the
smaller the impedance difference between each trace is likely to be. Maintaining an equal length
and parallel ground trace for the total length of each clock ensures a low inductance ground return
and produces the minimum current path loop area. (The parallel ground trace has lower inductance
than the ground plane because of the mutual inductance of the current in the clock trace.)
®
Intel 810A3 Chipset Design Guide
power with the widest signal trace or mini-plane as possible. Place decoupling caps
TT
and ground in the vicinity of the connector pins.
TT
Advanced System Bus Design
5-17