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(6)
Wait signal (WAIT)
The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing
to transmit or receive data (i.e., is in a wait state).
Setting the SCLn pin to low level notifies the communication partner of the wait status. When wait status has
been canceled for both the master and slave devices, the next data transfer can begin (n = 0, 1).
(a) When master device has a nine-clock wait and slave device has an eight-clock wait
Master
IIC0
SCL
Slave
IIC0
SCL
ACKE
Transfer lines
SCL
SDA
Remark
n = 0, 1
358
CHAPTER 10
SERIAL INTERFACE FUNCTION
Figure 10-32. Wait Signal (1/2)
(master: transmission, slave: reception, and ACKEn = 1)
Master returns to high
impedance but slave
is in wait state (low level).
6
7
8
9
Wait after output
of eighth clock.
H
6
7
8
D2
D1
D0
User's Manual U13850EJ6V0UD
Wait after output
of ninth clock.
IIC0 data write (cancel wait)
1
FFH is written to IIC0 or WREL is set to 1.
9
1
ACK
D7
2
3
2
3
D6
D5
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