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Slave address
register n (SVAn)
SDAn
Noise
eliminator
register n (IICn)
N-ch open-drain
output
Start condition
Stop condition
SCLn
Noise
Serial clock counter
eliminator
Serial clock controller
N-ch open-drain
output
fxx
Prescaler
TMx output
CLDn DADn SMCn DFCn CLn1 CLn0
Remarks 1. n = 0, 1
2. TMx output
n = 0: TM2 output
n = 1: TM3 output
CHAPTER 10
SERIAL INTERFACE FUNCTION
Figure 10-23. Block Diagram of I
Internal bus
IIC control register n
(IICCn)
IICEn
LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn
Set
Clear
Match signal
SO latch
IIC shift
D Q
CLn1,
CLn0
Data hold time
correction
circuit
ACK detector
detector
detector
wait controller
CLXn
IIC clock selection
IIC function expansion
register n (IICCLn)
register n (IICXn)
User's Manual U13850EJ6V0UD
2
C
IIC status register n (IICSn)
MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn
Start
condition
generator
ACK output
circuit
Wakeup controller
Interrupt request
signal generator
Serial clock
IICCEn1 IICCEn0
IIC clock expansion
register n (IICCEn)
Internal bus
INTIICn
Bus status
detector
STCFn IICBSYn STCENn IICRSVn
IIC flag register n
(IICFn)
335
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