Block Diagram Of P10 To P12, P14, And P15 - NEC V850/SB1 User Manual

(c) Port 1 function register (PF1)
PF1 can be read/written in 8-bit or 1-bit units.
After reset: 00H
7
PF1 0
PF1n
0
1
Note Bit 3 is fixed as a normal output.
(3) Block diagram (Port 1)
WR
PU
RD
WR
PF
WR
PORT
WR
PM
Note The SDA0 and SCL0 pins are available only in the Y versions (products with on-chip I
Remarks 1. PU1: Pull-up resistor option register 1
PF1: Port 1 function register
PM1: Port 1 mode register
RD: Port 1 read signal
WR: Port 1 write signal
2. n = 0 to 2, 4, 5
CHAPTER 14
R/W Address: FFFFF0A2H
6 5
0 PF15
Control of normal output/N-ch open-drain output (n = 0 to 2, 4, 5)
Normal output
N-ch open-drain output
Figure 14-2. Block Diagram of P10 to P12, P14, and P15
PU1
PU1n
Selector
PF1
PF1n
Output latch
(P1n)
PM1
PM1n
Alternate function
User's Manual U13850EJ6V0UD
PORT FUNCTION
4 3
Note
PF14 0 PF12
2 1 0
PF11 PF10
V
DD
P-ch
V
DD
P10/SI0/SDA0 Note
P-ch
P11/SO0
Note
P12/SCK0/SCL0
P14/SO1/TxD0
N-ch
P15/SCK1/ASCK0
2
C).
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