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The slave address and the eighth bit, which specifies the transfer direction as described in (3) Transfer
direction specification below, are written together to the IIC shift register (IICn) and are then output. Received
addresses are written to IICn (n = 0, 1).
The slave address is assigned to the higher 7 bits of IICn.
(3)
Transfer direction specification
In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When
this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to
a slave device. When the transfer direction specification bit has a value of 1, it indicates that the master device
is receiving data from a slave device.
SCLn
SDAn
INTIICn
Note INTIICn is generated if a local address or extension code is received during slave device operation.
Remark
n = 0, 1
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CHAPTER 10
SERIAL INTERFACE FUNCTION
Figure 10-11. Transfer Direction Specification
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2
3
4
AD6
AD5
AD4
AD3
User's Manual U13850EJ6V0UD
5
6
7
8
9
AD2
AD1
AD0
R/W
Transfer direction specification
Note
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