Appendix Erevision History - NEC V850/SB1 User Manual

32-bit single-chip microcontroller
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The following table shows the revision history up to this edition. The "Applied to:" column indicates the chapters of
each edition in which the revision was applied.
Edition
4th
Modification of 1.2.3 Ordering information (V850/SB1)
Modification of 1.3.3 Ordering information (V850/SB2)
Modification of description in 2.3 (5) P40 to P47 (Port 4)
Modification of description in 2.3 (6) P50 to P57 (Port 5)
Modification of description in 2.3 (7) P60 to P65 (Port 6)
Modification of description in 2.3 (9) P90 to P96 (Port 9)
Modification of Caution in 2.3 (11) (b) (ii) WAIT (Wait)
Addition of 2.3 (14) CLKOUT (Clock Out)
Addition of 5.8 (1) Acknowledging interrupt servicing after execution of EI
instruction
Addition of 6.6 Notes on Power Save Function
Modification of Caution in 7.1.3 (2) Capture/compare registers n0 (CR00, CR10)
Modification of Caution in 7.1.3 (3) Capture/compare registers n1 (CR01, CR11)
Modification of Figure 7-34 Data Hold Timing of Capture Register
Addition of 7.2.7 (6) (c) One-shot pulse output function
Modification of Figure 11-2 A/D Converter Mode Register 1 (ADM1)
Addition of description in 11.5 Low Power Consumption Mode
Addition of Caution in CHAPTER 18 FLASH MEMORY
Addition of Table 19-5 Acknowledge Signal Output Condition of Control Field
Addition of description 19.1.8 Bit format
Modification of Caution in 19.3.2 (1) (a) Communication enable flag (ENIEBUS)
Addition of Note in Figure 19-18 Timing of INTIE2 Interrupt Generation in Locked
State (for (4) and (5))
Addition of Remark in 19.3.2 (6) IEBus telegraph length register (DLR)
Addition of Remark in 19.3.2 (7) IEBus data register (DR)
Addition of description in 19.3.2 (7) (a) When transmission unit
Modification of description in 19.3.2 (8) (a) Slave request flag (SLVRQ)
Addition of Caution in 19.3.2 (8) (b) Arbitration result flag (ARBIT)
Addition of description for Caution in 19.3.2 (8) (e) Lock status flag (LOCK)
Addition of Table 19-8 Reset Condition of Each Flag of ISR Register
Addition of 19.4.3 Communication error source processing list
Modification of Figure 19-34 Master Transmission (Interval of Interrupt
Occurrence)
Modification of Figure 19-35 Master Reception (Interval of Interrupt Occurrence)
Modification of Figure 19-36 Slave Transmission (Interval of Interrupt Occurrence)
Modification of Figure 19-37 Slave Reception (Interval of Interrupt Occurrence)
664
APPENDIX E
REVISION HISTORY
Major Revisions from Previous Edition
User's Manual U13850EJ6V0UD
(1/5)
Applied to:
CHAPTER 1
INTRODUCTION
CHAPTER 2 PIN
FUNCTIONS
CHAPTER 5 INTERRUPT/
EXCEPTION
PROCESSING FUNCTION
CHAPTER 6 CLOCK
GENERATION FUNCTION
CHAPTER 7
TIMER/COUNTER
FUNCTION
CHAPTER 11 A/D
CONVERTER
CHAPTER 18 FLASH
MEMORY
CHAPTER 19 IEBus
CONTROLLER
(V850/SB2)

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