Interrupt Source List - NEC V850/SB1 User Manual

19.4.2 Interrupt source list

The interrupt request signals of the internal IEBus controller in the V850/SB2 can be classified into vector interrupts
and DMA transfer interrupts. These interrupt request signals can be specified through software manipulation.
The interrupt sources are listed below.
Interrupt Source
Timing error Master/slave
Parity error Reception
NACK reception Reception
(Transmission)
Underrun error Transmission
Overrun error Reception
Start interrupt Master
Slave
Status transmission Slave
End of communication Transmission
Reception
End of frame Transmission
Reception
Transmit data write Transmission
Receive data read Reception
Note If DMA transfer or software manipulation is not executed.
CHAPTER 19 IEBus CONTROLLER (V850/SB2)
Table 19-9. Interrupt Source List
Condition of Generation
Unit Field
All fields
Other than data
(individual)
All fields
(broadcasting)
Other than data
(individual)
Data
Data
(broadcasting)
Slave/address
Slave/address
Control
Data
Data
Data
Data
Data
Data
User's Manual U13850EJ6V0UD
CPU Processing after
Generation of Interrupt
Undo communication
processing
Slave request judgment
Contention judgment
(If loses, remaster processing)
Communication preparation
processing
Slave request judgment
Communication preparation
processing
Refer to transmission
processing example such as
slave status.
DMA transfer end processing
DMA transfer end processing
Receive data processing
Retransmission preparation
processing
Re-reception preparation
processing
Note
Reading of transmit data .
Note
Reading of received data
Remark
Communication error is OR
output of timing error, parity
error, NACK reception,
underrun error, and overrun
error
Interrupt always occurs if loses
in contention during master
request
Generated only during slave
request
Interrupt occurs regardless of
slave transmission enable flag
Interrupt occurs if NACK is
returned in the control field.
Set if SCR is cleared to 0
Set if CCR is cleared to 0
Set after transfer transmission
data to internal shift register
This does not occur when the
last data is transferred.
Set after normal data reception
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