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Interrupt/exception table
The V850/SB1 and V850/SB2 increase the interrupt response speed by assigning handler addresses
corresponding to interrupts/exceptions.
The collection of these handler addresses is called an interrupt/exception table, which is located in the internal
ROM area. When an interrupt/exception request is granted, execution jumps to the handler address, and the
program written at that memory address is executed.
corresponding addresses are shown below.
Start Address of
Interrupt/Exception Table
00000000H
00000010H
00000020H
00000040H
00000050H
00000060H
00000080H
00000090H
000000A0H
000000B0H
000000C0H
000000D0H
000000E0H
000000F0H
00000140H
00000150H
00000160H
00000170H
00000180H
00000190H
000001A0H
000001B0H
000001C0H
Note Available only in the Y versions (products with on-chip I
CHAPTER 3
CPU FUNCTIONS
Table 3-3. Interrupt/Exception Table
Interrupt/Exception Source
RESET
NMI
INTWDT
TRAP0n (n = 0 to F)
TRAP1n (n = 0 to F)
ILGOP
INTWDTM
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
INTWTNI
INTTM00
INTTM01
INTTM10
INTTM11
INTTM2
INTTM3
INTTM4
INTTM5
User's Manual U13850EJ6V0UD
The sources of interrupts/exceptions, and the
Start Address of
Interrupt/Exception Table
000001D0H
000001E0H
000001F0H
00000200H
00000210H
00000220H
00000230H
00000240H
00000250H
00000260H
00000270H
00000280H
00000290H
000002A0H
000002B0H
000002C0H
000002D0H
000002E0H
000002F0H
00000300H
00000310H
00000320H
00000330H
2
C).
Interrupt/Exception Source
INTTM6
INTTM7
Note
INTIIC0
/INTCSI0
INTSER0
INTSR0/INTCSI1
INTST0
INTCSI2
Note
INTIIC1
INTSER1
INTSR1/INTCSI3
INTST1
INTCSI4
INTIE1 (V850/SB2 only)
INTIE2 (V850/SB2 only)
INTAD
INTDMA0
INTDMA1
INTDMA2
INTDMA3
INTDMA4
INTDMA5
INTWTN
INTKR
109
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